LT1948 1 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. n tft-lcd notebook display panels n tft-lcd desktop monitor display panels n digital cameras n handheld computers , ltc and lt are registered trademarks of linear technology corporation. n complete solution under 1.2mm n develops three outputs from a 3.3v or 5v supply n externally programmable v on delay n fixed frequency low noise outputs n all ceramic capacitors n operates at 3mhz switching frequency n fast transient response n few external components required n 2.6v to 6v input range n tiny 8-lead msop package applicatio s u features descriptio u typical applicatio u dc/dc converter for tft-lcd panels august 2000 final electrical specifications l2, 2.2 h bat54s d3a d3b d1 mbrm120 c5 1 f c4 0.22 f c2 2.2 f c1 2.2 f v in 2.5v to 6v av dd 8v 260ma v on 23v 10ma 1948 f01 v off ?v 15ma fb1 sw1 LT1948 v in v on c t sw2 vo2 c6 22nf c1, c2: taiyo yuden lmk212bj225 c3: taiyo yuden tmk316bj224 c4: taiyo yuden emk212bj224 c5: taiyo yuden lmk212bj105 l1?3: taiyo yuden lb2012-2r2 gnd l1, 2.2 h d2 cmdsh-3 l3 2.2 h c3 0.22 f r1 53.6k r2 10k figure 1. 3.3v powered tft-lcd bias generator 2ms/div 1948 ta01a v in 5v/div v on 20v/div av dd 10v/div v off 10v/div start-up waveforms the lt ? 1948 is a highly integrated multiple output dc/dc converter designed for use in tft-lcd panels. the device contains two independent switching regulators: the main regulator has an adjustable output voltage with an internal 1.1a switch that can generate a boosted voltage as high as 30v while the second regulator generates 23v at up to 10ma for positive bias. a simple level-shift charge pump off the main switch node generates the negative bias voltage. an external capacitor sets the delay time from av dd reaching final value to 23v appearing at the v on pin. the 3mhz switching frequency allows the use of tiny low profile chip inductors and capacitors throughout, provid- ing a low noise, low cost total solution with all components under 1.25mm in height. the device operates from an input range of 2.6v to 6v and is available in an 8-lead msop package. not recommended for new designs contact linear technology for potential replacement
LT1948 2 v in voltage ................................................................ 8v c t voltage .................................................................. 6v sw1, sw2 voltage .................................................. 36v fb voltage ................................................................. 3v v on , vo2 voltage ..................................................... 30v operating temperature range (note 2) .. C 40 c to 85 c lead temperature (soldering, 10 sec).................. 300 c order part number ms8 part marking t jmax = 125 c, q ja = 200 c/w consult factory for industrial and military grade parts. ltnr LT1948ems8 absolute axi u rati gs w ww u package/order i for atio uu w (note 1) electrical characteristics note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the LT1948 is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C 40 c to 85 c operating the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 3.3v unless otherwise specified. symbol conditions min typ max units supply current not switching 7 13 ma reference voltage 1.26 v reference line reg 2.7v < v in < 8v 0.01 %/v c t source current v fb1 = 1.3v 4.5 5.5 6.5 m a c t voltage to turn on q3 1.25 1.28 1.30 v fb1 voltage to begin c t charge 1.17 1.20 1.23 v sw1 current limit (note 3) 1.2 1.5 a sw2 current limit (note 3) 0.5 0.8 a sw1 saturation voltage i sw1 = 800ma 350 410 mv sw2 saturation voltage i sw2 = 300ma 250 300 mv oscillator frequency l 2.4 3.2 3.6 mhz maximum duty cycle 70 75 90 % 0 c t a 85 c l 69 % C40 c t a 0 c l 67 % vo2 pin resistance measured to ground 400 k w sw1, sw2 error amp gain 100 v/v sw1, sw2 error amp gm 50 m a/v fb1 regulation voltage 1.240 1.260 1.280 v l 1.230 1.285 v fb1 line regulation 2.7v < v in < 8v 0.01 0.05 vo2 regulation voltage 22 23 24 v v on switch drop vo2 = 25v, 7ma load from v on , c t voltage >1.30v 200 260 mv sw1 leakage current switch off, sw1 voltage = 3.3v 0.01 5 m a sw2 leakage current switch off, sw2 voltage = 3.3v 0.01 2 m a 1 2 3 4 fb1 c t sw1 gnd 8 7 6 5 v on vo2 sw2 v in top view ms8 package 8-lead plastic msop temperature range are assured by design, characterization and correlation with statistical process controls. note 3: current limit guaranteed by design and/or correlation to static test.
LT1948 3 pi fu ctio s uuu fb1 (pin 1): feedback pin for first switcher. connect resistor divider tap here. set av dd according to av dd = 1.26v(1 + r1/r2). c t (pin 2): timing capacitor pin. connect a 22nf capacitor from c t to ground to program a 3ms delay from fb1 reaching 1.26v to v on turning on. sw1 (pin 3): av dd switch node. connect inductor and d1 here (see figure 1). minimize trace area at this pin to keep emi down. gnd (pin 4): ground. connect directly to local ground plane. v in (pin 5): input supply pin. must be bypassed with a ceramic capacitor close to the pin. sw2 (pin 6): vo2 switch node. connect inductor and d2 here. minimize trace area at this pin to keep emi down. vo2 (pin 7): sense pin for 23v output. connect to vo2 output capacitor. this node is also internally connected to the emitter of q3 (see block diagram), the high side switch between vo2 and v on . v on (pin 8): this is the delayed 23v output. v on becomes 23v after the internal timer times out. to best understand operation of the LT1948, please refer to the LT1948 block diagram. the device contains two switching regulators, a timer and a high side switch. three outputs can be generated: an adjustable av dd output, a charge-pumped inversion of the av dd output, called v off , and a 23v/15ma output, called v on . q3 keeps v on off for an externally set time interval, set by a capacitor connected to the c t pin. the switching frequency of both switchers is 3mhz, set internally. the switchers are current mode and are inter- nally compensated. the main av dd switcher is current limited at 1.5a, while the second v on switcher is limited to 800ma. they share the same 1.26v reference voltage. 1948 f02 1 2 8 7 3 4 6 5 l3 r1 r2 c1 d1 v on v in v off d4b d3a l1?2 c4 c3 d2 c2 c6 gnd av dd operatio u figure 2. recommended component placement when the input voltage is below approximately 2.4v, an undervoltage lockout circuit disables switching. when av dd is less than its final voltage, q4 is turned on, holding the c t pin at ground. when av dd reaches final value, q4 lets go of the c t pin, allowing the 5.5 m a current source to charge the external capacitor, c t . when the voltage on the c t pin reaches 1.25v, q3 turns on, connect- ing vo2 to v on . capacitor value can be calculated using the following formula: c = (5.5 m a ? t delay )/1.25v a 22nf capacitor results in approximately 3ms of delay.
LT1948 4 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com ? linear technology corporation 2000 1948i lt/tp 0800 4k ? printed in usa related parts part number description comments lt1949 600khz, 1a switch pwm dc/dc converter 10v at 175ma from 3.3v input lt1317 2-cell micropower dc/dc with low-battery detect 3.3v at 200ma from 2-cell input lt1308b 600khz single cell step-up regulator 5v at 1a from a 1-cell li-ion battery lt1615 micropower step-up regulator in sot-23 20v at 12ma from 2.5v input, 5-lead sot-23 package lt1930 1.2mhz, step-up regulator in sot-23 5v at 480ma from 3.3v, 5-lead sot-23 package slope 2 + q2 0.03 1948bd sw2 + + r s osc q slope 1 + q1 0.01 sw1 + + r s osc v in q + 8 a osc slope 1 3mhz oscillator ref ref 1.26v reference and undervoltage lockout slope 2 ref ref q4 q3 28mv + v on c t vo2 fb1 + ref v in gnd block diagra w
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